Within the context of data acquisition devices such as digital storage oscilloscopes (DSOs) utilizing very high speed analog-to-digital (“A/D”) converters, the effect of memory bandwidth constraints becomes a significant design factor. Specifically, memory devices available today cannot store data as rapidly as the data is produced by very high speed A/D converters. Moreover, in an interleaving technique, each of a plurality of A/D converters operates to digitize a common signal under test (SUT) according to respective phase-staggered clock signals to produce respective interleaved sample streams. Acquisition data provided by each of the A/D converters is stored in memory within respective demultiplex (“demux”) processing elements. The acquisition data must be de-interleaved such that samples from each demultiplex processing element are collected and placed in their correct order according to sample time so that additional processing may be performed on the de-interleaved sample stream (e.g., rasterization). Unfortunately, each of the demultiplexer processing elements lacks a contiguous time record of the entire acquisition.
In current oscilloscopes the deinterleaving function is performed via a shared multi-drop bus that receives sample data from each of the demux processing elements. The sample data driven onto the multi-drop bus by the demux processing elements is de-interleaved by an additional processing unit (e.g., a processor or memory device cooperating with the bus) to provide thereby a de-interleaved acquired sample stream. Unfortunately, due to device loading and bandwidth constraints, the multi-drop bus architecture is unable to cope with increasing A/D converter speeds, increased numbers of demux processors and other system demands.